CPUMSR help
Version: 0.88
Prepared by: Petr Koc
AMD K7 (Athlon) class
Supported CPU cores: K7, K75, Spitfire, Thunderbird, Palomino,
Thoroughbred, Barton
Note: Some features are supported only on newer CPU cores.
Processor Name String
A 48 character string used by many programs to reference processor type
to end user. This is NOT representative of what BIOS detected. Name
String in no way affects programs functionality nor has it any
connection to reliability. It is just a string programmed by BIOS "for
pleasure", for Mr. Average to see in his operating system he has Athlon
XP 2000+ for example.
Note that Name String is allowed to have 48 characters while the last
one should be NUL. Otherwise some programs fail to display it correctly
or they just crash. I allow to have the 48th char anything you want, but
please understand that safe Name String is 47 characters in lenght.
FSB to Core Clock Multiplier
Represents startup FID code (multiplier) used to program chipset FID
values.
Major / Minor Mask Set Revision Number
Specifies what mask was used in the factory while producing this CPU.
Some masks can be better in terms of temperature, overclocking ect.
There is also a theory that superlocked CPUs have specific Major / Minor
Mask Set Revision.
Halt Disconnect Clock Divisor
Tells the CPU how much should clock be reduced while entering C1 Halt
power saving mode. The resulting frequency is nominal frequency divided
by divisor (for example 2000 MHz CPU with clock divisor of 16 runs at
125 MHz in Halt mode). C1 Halt mode is entered upon running privileged
instruction HLT - many 3rd party software cooling programs do this. For
proper functionality of C1 Halt mode it is necessary the chipset
disconnects Front Side Bus after receiving request generated by the
processor. Majority of K7 chipsets support this but on older
motherboards, this is often not enabled by default due to problems with
this feature. Those problems are usually in form of sound crackles,
lowered HDD performance, PCI problems ect.
For proper functionality of this feature, you need:
1. Chipset enabled FSB disconnect after Halt special system bus cycle
(set by BIOS, otherwise use WPCREDIT / WPCRSET).
2. Set Halt Disconnect Clock Divisor (set by BIOS to some default value,
different on many motherboards).
Higher divisors result in lower frequency what turns in somewhat
lower temperature and lower power consumption. On the other hand, those
higher divisors tend to cause problems described above and sometimes
even to systems hangs. Problems may be fixed either totally by disabling C1 Halt
mode by tools like WPCREDIT / WPCRSET or sometimes by setting divisor to
8.
The result of enabling C1 Halt mode can be as much as 15 degrees
Celsius temperature decrease. Different divisors have somewhat lower
effect, the difference between 8 and 512 can be 5 degrees at most.
Stop Grant Clock Divisor
This is the same as for Halt Disconnect Clock Divisor with the
difference that this one sets frequency divisor for C2 Stop Grant power
saving mode. The effect of power requirements reduction is the same as
in case of C1 Halt mode, but there are few differences. First - chipset
has to be set to disconnect FSB upon receiving Stop Grant request, not
Halt request. On many chipsets, there are separate bits for Halt and for
Stop Grant, so be sure to set the right one. Second - you do not need
any program to enter to C2 Stop Grant state because Windows 2000 / XP
have already integrated mechanism that does this.
Problems associated with C1 Halt applies also to C2 Stop Grant, but
since you do not need any 3rd party program, less resources are used and
often performance is somewhat higher and reliability better.
Clock Change Timing
This settings affect time between clock changes inside the CPU while
entering to / from C1 Halt or C2 Stop Grant modes. Faster settings mean
lower latencies and therefore higher performance and better resistance
to problems with sound cards, HDD performance ect. But on the other
hand, faster settings impose higher requirements on internal clock
generator. Often this can result in clock not to be multiplier correctly
but with some deviation - for example 10x 100 MHz being 1030 MHz, not
1000 MHz. If you experience problems with stability, set this to normal
of Slow.
APIC bus messages during clock ramp down
APIC stands for Advanced Programmable Interrupt Controller, an IRQ
controller integrated into CPU. This was developed for multi-CPU systems
to synchronize each processor, but today it is often used on single-CPU
systems to get more than 16 IRQs. If your system reports more than 16
IRQs, you have APIC and have it enabled. Those settings control whether
the CPU should reject any messages while being in C1 Halt or C2 Stop
Grant state. If you have problems with those low power modes, try to set
Do not reject.
System Call Extensions
Just experimental because this should be set by OS to make any use of
this feature.
System Data ECC Checking
Enables data transfers on Front Side Bus to be protected by ECC. Often
doesn't work on many chipsets.
TLB Force Cacheable
TLB is Translation Look-Aside Buffer, a part of memory where translated
addresses are stored. By enabling this feature, you force this table
to be cached. You can get quite large performance improvement while
using memory intensive programs by doing so. If you experience problems
(not expected), disable it.
Current Voltage
Tells what CPU requires through SoftVID pins. On majority of desktop
motherboards, those pins are not connected, therefore this has no
information value on such systems, it only tells you what combination is
set on five processor's pins that are however not connected.
Note: Mobile VID codes are used, those differ from Desktop VID codes.
Startup Voltage
What voltage did the CPU start at, eg. L11 bridges settings. This
may be higher than maximum in rare cases.
Maximum Voltage
Maximum voltage you can set through PowerNow! on the fly voltage
transition, eg. L8 settings. You can never set higher value than this by
PowerNow! because CPU compares required voltage with this and if higher,
sets this.
Current Multiplier
Tells what multiplier is currently used by CPU.
Startup Multiplier
Tells what multiplier CPU starts at, eg. L3 bridges settings. This can
in rare cases be higher than maximum.
Maximum Multiplier
This is the maximum multiplier you can set by PowerNow! on the fly
multiplier transition, eg. L6 settings. You can never set higher value
than this by PowerNow! because CPU compares required multiplier with
this and if higher, sets this.
Voltage Adjustments
Two values are possible - Supported and Not supported. If you want to
use PowerNow! to change voltage on the fly, this field must report
Supported. This does not mean your system can change voltage, only that
CPU itself supports it - but you also need motherboard support.
Frequency Adjustments
The same as for Voltage Adjustments except this is for multiplier. For
multiplier change to work, chipset has to be set to respond to
FID_Change command (some chipsets like nForce 2 do not support this
feature).
Number of system bus FID/VID stabilization cycles
While changing voltage or multiplier on the fly, processor enters Stop
Grant state for required FSB clock cycles. This is for voltage regulator
/ internal clock generator to stabilize after change. Recommended value
is 10000 clock cycles when FSB is operating at 100 MHz (eg. with 10ns
period). While increasing FSB clock, please increase this value also -
for 200 MHz (eg. with 5ns period), it is recommended to set this
to 20000 clock cycles. Some systems may need higher or lower values,
this is system and CPU specific.
Multiplier Adjustments
On processors supporting PowerNow!, this allows changing voltage and
multiplier. Motherboard support is required for both voltage (SoftVID
pins connected to motherboard voltage control logic) and multiplier
(chipset has to support FID Change Command and this has to be enabled).
Frequency Report
The CPU's frequency shown on the Frequency & Voltage Control page is how
Time Stamp Counter (TSC) increased. TSC is a counter of clock ticks
performed by processor since start. Values lower than nominal frequency
(eg. 50 MHz or so) mean your system is Halt or Stop Grant modes enabled
and that those modes are operational. This is because when your CPU ran
half a second at full speed (let say 2000 MHz) then the remaining half a
second was in Stop Grant (with frequency let say 250 MHz), the result is
an weighted average of those (in this case (2000 + 250) / 2 = 1125 MHz).
This calculation is effective only for faster Clock Change Timing
settings because, for some reason, for slower settings TSC increases all
the time just as if CPU is running at full speed.
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