Elpida produziert 1 GHz DDR-RAM

Hartware berichtet, dass Samsung zur Zeit mit 800 MHz-Chips in kleinen Stückzahlen die schnellsten Chips fertigt. Die Massenproduktion erreicht derzeit maximal 700 MHz (genutzt für die GeForce4 Ti4600). Wenn Elpida die eigenen 1 GHz-Chips bald in großen Stückzahlen herstellen kann, liegt man also weit vor der Konkurrenz. Pressemitteilung Elpida Memory Develops World's Fastest Data Rate TOKYO, JAPAN, June 17, 2002 - Elpida Memory, Inc. (Elpida), announced today the development of new circuit technologies and a low-impedance hierarchical I/O architecture that enables 1 Gigabit per second (Gbps) per pin operation with a 1.8 Volt (V) power supply in a multi-Gb DRAM. The results were verified with a 0.13 micron 512 Megabit DDR-II SDRAM, and represent performance that is 7.5 times that of Single-Data-Rate PC133 SDRAM, and a 75% improvement over DDR 266. On June 14, Elpida Memory presented two papers on these technologies at 2002 symposium on VLSI Circuits in Honolulu, Hawaii. To achieve 1 Gbps data rates at 1.8 V requires precisely synchronized regenerated clocking with less than 30 ps misalignment, and high-integrity output data signals for a maximized valid data window. Such performance also requires a read/write cycle time of less than 4 ns and an access time of less than 8 ns. Elpida\'s unique technology satisfies these requirements, providing more than enough bandwidth for high-end workstations and PCs that require the maximum 533 Mbps operation specified by DDR-II at 1.8 V. The technology will also accommodate the highest data rates of the next-generation DRAM specification, DDR-III. "By combining both high-speed and low-voltage operations, Elpida's advanced technologies and architectures are driving memory bandwidth to never-before-seen levels," said Jun Kitano, director of Technical Marketing for Elpida Memory (USA) Inc. "As a result, Elpida customers will experience the world's fastest data rates to accommodate the high-end systems of today as well as the DDR-III implementations of tomorrow." Elpida combines the highest performance device and process technologies with advanced new circuit technologies that meet the challenges of next generation DRAM technologies: Output Skew Control: to eliminate output skew caused by device characteristics, operation voltage, and temperature fluctuations. Elpida has developed: Low-power, high-resolution digital delay-locked-loop (DLL): Includes clock regeneration circuits to align the output data timing with the input clocking at 1.6 V operation or lower. Output buffer circuit: Adjusts the output buffer impedance while maintaining the slew rate of output signals. These new circuits can reduce the output skew to as low as 10 ps, enabling the component to realize its potential of 1 Gbps. Reduced Cycle and Access Time: To reduce read/write cycle time and access time, Elpida has designed a new architecture that includes: Low-impedance hierarchical I/O architecture that calls for routing divided I/O lines over the memory cells with no tightening of the wiring pitch. This reduces the load of I/O lines by 50% and enables a 2.2 ns reduction of the read/write cycle time. Distributed data transfer scheme prioritized by ordered data. The new architecture achieves 4 ns read/ write cycle time, which is a 45% reduction in access time to accommodate the 1 Gbps data rate of the DDR-II architecture. The design of computer systems is constantly improving both in terms of performance and power consumption, and 1.8 V DDR-II SDRAM is a necessary solution for the main memory component of these systems. Elpida's new circuit technologies can be used to fabricate the world's first commercial DDR-II SDRAM from Elpida and will hasten the development of next-generation DDR-III specifications into the mainstream of DRAM applications.